| 摘要 |
<p>The invention provides data processing duplication and internal error checking within an integrated circuit chip at intermediate points along the logic chain. In one aspect of the invention. duplicate functional logic within the chip is utilized together with multiple fault detectors to provide error checking of the primary logic chain, mechanical interconnection failures, and power and clock pulse checking. The detectable failures are both transient and hard failures. Other problems are in addition resolvable by utilization of duplicate complementary logic in place of duplicate functional logic, such other problems including chip contamination during manufacture, mask problems and functional design problems. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. These encoded error signals are routed to a special error handling chip which receives encoded error signals from a large number of places, such as a group of chips or circuit cards, and by correlating the information contained in the encoded error signals is able to identify the source of the error as a particular VLSI chip, the interconnections between VLSI chips, a particular circuit card, a power supply line to a circuit card or a group of such cards. or other faults.</p> |
