发明名称 MULTIPLE INFORMATION PROCESSING SYSTEM
摘要 PURPOSE:To reconstitute a multiprocessor even when one CPU is troubled by providing each of CPUs, sharing a main storage device, with two pairs of input and output ports for a loop interface and by alternating the return flow directions of information in response to a control signal. CONSTITUTION:Central processing units CPU0-CPU2 are connected in a loop and use a main storage device MS in common. In triple multiple operation, each CPU normally uses the connection ports of the input port I1 and output port O1 of a loop interface IF for operation to circulate information, required among the CPUs, in a loop shape. For example, if the CPU0 is troubled, the CPU1 uses the connection ports of the input port I2 and output port O1 of the loop IF by being switched by a system constitution controlling signal, and the CPU2 uses the connection ports of the input port I1 and output port O2, thereby circulating informatin between the CPU1 and CPU2 in the loop shape.
申请公布号 JPS57729(A) 申请公布日期 1982.01.05
申请号 JP19800073959 申请日期 1980.06.02
申请人 HITACHI LTD 发明人 MATSUURA TSUGUO
分类号 G06F13/14;G06F3/00;G06F11/20;G06F13/00;G06F15/16;G06F15/177 主分类号 G06F13/14
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