Low voltage serial to parallel to serial charge coupled device.

摘要

This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register (14) with stage gate electrode structures (30 to 36) that are interdigitated with the gate electrode structures of each last stage (38) of a plurality of parallel shift registers (12) to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order. This is done without employing a fixed voltage midway between the highest clock voltage and reference potential in the parallel register in what is commonly called a midway store to regulate the transfer of data to the interdigitated gate electrode structures.