| 摘要 |
PURPOSE:To reduce the phase modulation side band component, by cancelling the phase jitter of a variable frequency divider output of a phase detector, in a frequency synthesizer which reduces the side band noise of a voltage controlled oscillator. CONSTITUTION:An output of a voltage controlled oscillator 14 is fed to a programmable counter 21 and an output pulse width of the counter 21 is changed from the result of sequential operation by an operator 15, and a phase increment equivallent to the increment of a phase delay of a variable frequency divider 16 is given to an output of a reference frequency oscillator 11 which changes the output pulse width of a pulse width modulator 18. A ripple component is disappeared through cancel at the output of a phase detector 12 in the locked state of a phase locked loop, by applying the output of the pulse width modulator 18 and the output of the variable frequency divider 16. |
