| 摘要 |
PURPOSE:To enable the noise rejecting processing in real time, by making the noise rejecting processing through the hardware constitution in 6 sets of horizontal delay lines and two vertical delay lines and a logical circuit. CONSTITUTION:The 1st-6-th horizontal delay lines 5, 6, 8, 9, 11, 12 and the 1st and 2nd vertical delay lines 7, 10 constitute a 3X3 picture element matrix. Further, a signal outputted at the same time from an output terminal A of a binary video signal V, output terminals B, C, E, F, H, I of the 1st-6th horizontal delay lines, scans 9 video elements (not shown) at the same time. A logical circuit L consists of an 8-input AND gate 13, 8-input NOR gate 14, 2-input OR gate 15, inverter 16, 2-input OR gate 17, inverter 18, 2-input AND gates 19, 20, and 2-input OR gate 21. |
