| 摘要 |
PURPOSE:To omit the voltage supply line of a reset pulse generator by forming the same type impurity layer as a charge guide region directly under one gate electrode of an FET in a charge detecting layer, thereby enabling the simultaneous formation of the detector and the guide units. CONSTITUTION:With SiO2 films 2, 3 as masks P type ions are injected on a P type substrate 1 to form an N type layer 4, the film 3 is removed, and an insulating film 5 and a polysilicon gate electrode 6 are formed in an active region B. B ions are injected to supplement a part of the N type layer, a charge guide N<-> layer 7 in a CCD and an N<-> type layer 7' directly under the gate of a reset FET are formed in the active region A, and an N<-> type layer 7'' directly under the gate of the load FET is formed in the region B. An SiO2 film 8 is covered on the upper surface of the polysilicon electrode 6, a polysilicon gate electrode 9 is formed, and B is diffused to form an N<+> type layer 10. An SiO2 film 11 is eventually covered, and aluminum wires and connected to complete it. Accordingly to this configuration, the conductance of the lead FET is increased, its detecting responsiveness is accelerated, and the power voltage of the reset FET can be lowered, as well as can be supplied from common power lines, thereby unnecessitating additional components. |
