发明名称 ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To omit a multiplier by making an adder for operating the sum total of plural elements of an array processor usable for the purpose of multiplication. CONSTITUTION:A multiplying means consisting of plural multiple generating means 102-1-102-6 which divide multipliers to plural set and generate the multiples of multiplicands corresponding to the multipliers of the respective sets, carry save adders (CSA) 104-1 and 104-2 which add the outputs from these plural multiple generating means, and an adding means 109 which adds the sum outputs of the carry save adder means and carry outputs is provided, and further a register means which holds plural elements, a digit matching shift means which matches the digits of these plural elements and applies to the same to the above-mentioned carry save adder means, and a means which normalizes the output of the above-mentioned adding means are provided.
申请公布号 JPS56168276(A) 申请公布日期 1981.12.24
申请号 JP19800072486 申请日期 1980.05.30
申请人 HITACHI LTD 发明人 OMODA KOUICHIROU;NAGASHIMA SHIGEO;TORII SHIYUNICHI
分类号 G06F15/16;G06F7/52;G06F15/80;G06F17/10;G06F17/16 主分类号 G06F15/16
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