| 摘要 |
<p>A frequency shift keyed input (FSK) is applied to a phase detector (1) supported by a v.c.o. (3) which, in turn, receives the rectified signal via low pass filter (2) and a summing amplifier (7). This detector loop (PLL) supplies also a comparator (5) to produce the logic levels (DATA) at its output referenced to a stabilised voltage (VREF). An extra stabilising feedback loop consists of a signal line (D), a differential amplifier (8), a filter (9) which passes only very slow changes of signal level, and a sample-and-hold circuit (10) whose output contributes to the v.c.o. control input.S Metal oxide transistors (T1,T2) short out the filter sections at the beginning of each new reception period in order to allow the middle frequency voltage level to settle quickly. Then the transistors are slowly made non-conductive. The sample-and-hold circuit may be replaced by a digital store and a-d and d-a converters.</p> |
