| 摘要 |
In a gate array with a RAM which is disposed between first and second logic circuit blocks each of which having plural logic gates, by-pass signal lines which interconnect the logic circuit blocks are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines, such as word lines of the RAM, formed from a layer which is adjacent to the by-pass signal lines are disposed, with respect to a plan view layout arrangement of the main surface of a chip, so as to intersect the latter at right angles. In addition, interconnection pitches of signal lines in different wiring layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.
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