| 摘要 |
PURPOSE:To make the occupying area small and to enlarge the density of the inverter circuit with a clock gate by a method wherein FET's are provided in an insulated semiconductor region, and sources and drains of adjoining FET's are made to be held in common and are connected in series. CONSTITUTION:Three pieces n channel FET's 11, 13 and 14 one piece p channel FET 12 are integrated in an island-shaped single crystalline region made to grow epitaxially on a sapphire substrate 21, for example, to constitute the inverter with the clock gate. As for the source and drain regions of the adjoining n channel FET's of this circuit, diffusion layers 232, 233 are made to be held in common, the n type MOS and the p type MOS are connected in the form of p<+>n<+> diode 15, and are connected in series without providing wiring, and electric power source wires are connected to diffusion layers 231, 252 at both end parts. An input terminal is connected in common to the gates of the FET's 11, 13, an output terminal is connected to the diffusion layer 233 being held in common by the FET's 13, 14, a clock phi is inputted to gates of the FET's 13, 14 connected in common and Al electrodes are provided respectively. Accoridingly the inverter can be formed without providing connection wirings between respective FET's, and the density thereof can be en- hanced. |
