| 摘要 |
PURPOSE:To avoid a multiplex selection of a memory cell, by latching the address information to maintain a level of ''1'' or ''0''. CONSTITUTION:The address input information is applied to a gate A of a MOSFET6, and the potential of a node 3 is decided by the inverter ratio between MOSFETs 5 and 6. In the same way, the potential of a node 4 is decided by the inverter ratio between MOSFETs 8 and 9. The potential of the node 4 is positively fed back to the gate of the MOSFET, Tr7; and the potential of the node 3 is positively fed back to the gate of the MOSFET9. If the node 3 is ''1'', the node 4 is ''0''. The potential of the node 4 drives a driver, and the memory selection information is delivered from output teminals OUTs 3 and 4 of the driver to drive a decoder. The memory selection information delivered to the OUTs 3 and 4 of the driver is not turned to the intermidiate potential owing to a positive feedback. Thus a multiplex selection is never caused for a memory cell. |
