发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To increase the reading speed of a momery cell, by discharging the column line before selection of the memory cell and then stopping the discharge after detecting that the column line is discharged down to a prescribed level of potential. CONSTITUTION:When address signals A0-Am vary, the signal DI is turned to ''1'' to turn on transistors (TRs) 280-28m+1. Then a discharge is started for column line 200-20m and a control line B. When control lines B and RI are set at ''0'', the output of a NOR circuit 31 is set at ''1''. Thus the output signal DI of a pulse control circuit 29 is set at ''0'' to turn off TRs 280-28m+1. For instance, if a row line 191 and a column line 211 are designated with a cell 1811 selected each, the TR811 is turned on as far as no electron is injected into a floating gate of a transistor that forms this memory cell. Thus a column line 201 is discharged, and a signal of level ''0'' is delivered via an output circuit 27. The output is quickly set at the ''0'' level since the line 201 is already discharged.</p>
申请公布号 JPS56163587(A) 申请公布日期 1981.12.16
申请号 JP19800066254 申请日期 1980.05.19
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 IWAHASHI HIROSHI;ASANO MASAMICHI
分类号 G11C17/00;G11C7/12;G11C16/06;H01L21/8247;H01L29/788;H01L29/792 主分类号 G11C17/00
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