发明名称 MEMORY CONTROL DEVICE
摘要 PURPOSE:To realize a read/write with every 16 bits from an odd address for a 16-bit processor, by dividing a memory into two parts and then exchanging the read/write data between the 1st and 2nd memory sections. CONSTITUTION:When the data ''3456'' is written into an odd address (0001)16 of a memory ''34'' and ''56'' are written into exchangers 6 and 7 respectively via a bus 8. The address (0001)16 is stored in an address latch 3. As the lowest digit of the address is (1)16, i.e., an odd number, a cross connecton is secured between the exchangers 6/7 and the memories 2/1 and the contents ''34'' and ''56'' are supplied to the memories 2 and 1 respectively. The contents (0001)16 of the latch 3 receives an addition through a counter to be (0002)16. The lowest digits of (0001)16 and (0002)16 are (1)16 and (2)16 respectively to be turned into (0001)2 and (0010)2 in the form of a binary display. However, the lowest bit of the lowest digit of an address is not used for selection of the memories 1 and 2, (0001)2 and (0010)2 are shown as (000)2=(0)16 and (001)2=(1)16 respectively. The addresses which are applied to the memories 1 and 2 are (0001) 16 and (0000)16 each. Accordingly ''34'' and ''56'' are written into the address (0000)16 of memory 2 and the address (0001)16 of memory 1 respectively.
申请公布号 JPS56163594(A) 申请公布日期 1981.12.16
申请号 JP19800064442 申请日期 1980.05.15
申请人 CANON KK 发明人 MINAGAWA TAKASHI
分类号 G06F12/06;G11C8/12 主分类号 G06F12/06
代理机构 代理人
主权项
地址