发明名称 |
Semiconductor integrated circuit devices. |
摘要 |
A semiconductor memory device has memory cells 2 and decoder circuitry 3 disposed centrally thereof. A ground line 7 min extends around the memory cells 2 and the decoder circuitry 3. Control circuits 41 to 46 are disposed beneath or outwardly of the ground line 7 min . Signal lines 5 min for connecting the control circuits to one another are disposed outwardly of the control circuits 41 to 46. A power line 6 min is in turn disposed outwardly of the signal lines 5 min . This layout can provide for a reduction in the number of bridges required. |
申请公布号 |
EP0041844(A2) |
申请公布日期 |
1981.12.16 |
申请号 |
EP19810302502 |
申请日期 |
1981.06.05 |
申请人 |
FUJITSU LIMITED |
发明人 |
ITOH, HIDEO;YAMAUCHI, TAKAHIKO |
分类号 |
G11C11/41;G11C5/02;G11C5/14;G11C11/401;H01L21/822;H01L23/528;H01L27/02;H01L27/04;H01L27/10 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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