| 摘要 |
PURPOSE:To decrease the number of element FETs of a counter greatly by providing either power source or count pulses to the source sides of the FETs of an inverter circuit and by generating an output by connecting drain electrodes in common. CONSTITUTION:An N channel FET21 is connected in parallel to a P channel FET22 and count pulses Q1 and Q1' are supplied to their gate electrodes to constitute a transmission gate. Further, an inverter circuit is composed of the series FET circuit of N channel FETs 23 and 24, and another FET circuit of P channel FETs 25 and 26. A power source VDD or count pulse Q1 is connected or applied to the source side of the FET23, and a power source VSS or count pulse Q1' is connected or applied to the source side of the FET26 for biasing; and drain electrodes of the FETs 24 and 25 are connected in common to form the output terminal of the inverter circuit. Thus, the number of element FETs of a counter is greatly decreased. |
