| 摘要 |
<p>PURPOSE:To equalize the transmission speed of transmission to that of reception easily by selecting a start-stop synchronizing clock on the basis of read data by sending only one start bit from a transmission side and by reading the one bit at a reception side with a receiving clock having a high transmission speed. CONSTITUTION:Firstly, only one start bit is sent from a transmission side and this start bit is read by a start-stop synchronous receiving circuit 2 at a reception side. In this case, a clock CKn for receiving data having the highest transmission speed estimated in advance is used for the read and the read data is transferred to a microprocessor 5 via a bus 7. Then, the read data is judged by the processor 5 to discriminate its transmission speed and on the basis of the discrimination result, the selection of the clock of a clock selecting circuit 3 is controlled through an interface circuit 4 to equalize the transmission speed of transmission to that of reception easily.</p> |
