| 摘要 |
PURPOSE:To transfer data efficiently and economically, by controlling data transfer independently of a microprogram (muPG) after starting a control part by the muPG and by displaying the status detected at the transfer time to generate a muPG address. CONSTITUTION:The signal from a sequence control part 1 of a muPG starts a transfer control part 6 through a memory 3, a register 4, and decoder 5. When started by the muPG, the control part 6 controls the data transfer between a CPU and an I/O independently of the muPG and continues data transfer until a cause of transfer interruption occurs. If a cause of transfer impossibility occurs in the I/O, the control part 6 receives the signal indicating this state from the I/O and displays it on a status register RG9. A muPG address generator 10 tests the state of the RG9 periodically after the control part 6 is started; and when data transfer is interrupted to require another processing, a muPG address corresponding to the state is generated by this generator 10 and is transmitted to the control part 1. The control part 1 controls the system so that the control jumps to the generated address, and required processings are performed. |
