| 摘要 |
PURPOSE:To make the speed of data transfer fast by using one signal that a DMA controller generates as a request signal and holding the DMA controller in a wait state with the other signal, and resetting the wait state with a response signal and performing data transfer. CONSTITUTION:When handshake data transfer between a buffer RAM 4 and a host CPU 1 is performed, the DMA controller 2 is used and placed in the wait state with the signal that the DMA controller 2 generates, and the wait state of the DMA controller 2 is rest with an acknowledge (ACK) signal as a handshake request (REQ) signal. Consequently, the REQ signal for handshake control is generated automatically, the handshake data transfer is performed automatically without the intervention of a CPU 1, and the time from the return of the ACK signal to the output of a next REQ signal is minimized, thereby improving the transfer speed of data. |
