发明名称 |
Schmitt trigger circuit with a hysteresis characteristic. |
摘要 |
<p>Disclosed is a schmitt trigger circuit having an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation, comprising in its input stage a multi-emitter transistor (T11) and in its output stage a second transistor (T2). The multi-emitter transistor comprises a first emitter (E1) and a second emitter (E2). The first emitter is associated with a switching operation in response to the input voltage (Vin) applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor (T2) through the base of the multi-emitter transistor (T11) to the ground. By using the multi-emitter transistor, the input current (I1L) does not greatly increase as the input voltage (Vin) falls. </p> |
申请公布号 |
EP0041363(A1) |
申请公布日期 |
1981.12.09 |
申请号 |
EP19810302350 |
申请日期 |
1981.05.28 |
申请人 |
FUJITSU LIMITED |
发明人 |
ENOMOTO, HIROMU;MITONO, YOSHIHARU;YASUDA, YASUSHI;IMAIZUMI, TAKETO;OHTA, HIROSHI |
分类号 |
H03K3/2893;H03K5/08;(IPC1-7):03K3/295 |
主分类号 |
H03K3/2893 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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