| 摘要 |
A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and synchronizing it with a clock signal associated with a StarLAN coded data transceiver includes a synchronizer start circuit (32), a counter circuit (34), and a pattern detector circuit (36). The synchronizer start circuit (32) is responsive to the complement of the data input signals and the clock signal for generating a start signal which is synchronized with the clock signal. The counter circuit (34) is responsive to the start signal and the complement of the clock signal for generating a gated clock signal. The pattern detector circuit (36) is responsive to the start signal, the data input signals and the gated clock signal for sampling of the data input signals and for generating a synchronized output signal upon detection of a predetermined data sequence indicative of the preamble pattern. |
