发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To easily expand the depletion layer and to obtain a high withstand voltage for the planar type transistor used on subject semiconductor device by a method wherein the annular groove, protected by an insulating layer from the surface of a substrate, is provided in the collector region located around the connected section of a base collector. CONSTITUTION:The NPN (PNP) transistor of a planar type is formed by providing a P(N) type base layer 2 and an N(P) type emitter layer 3 on an N(or P) type substrate 1. Within the expanding range of the depletion layer 8 located outside the connected surface of the base collector, the annular groove 4 surrounding the junction part is provided and a construction is formed in such manner that the insulating layer 5 is protected by having it buried in the groove 4. Through these procedures, the depletion layer 8 of the collector can be spread out over the groove section 4, and said spreading section of the layer 8 is not terminated on the surface adjacent to the connected surface, the breakdown voltage close to the bulk can be obtained and the transistor of high withstand voltage can be obtained.
申请公布号 JPS56158474(A) 申请公布日期 1981.12.07
申请号 JP19800062451 申请日期 1980.05.12
申请人 NIPPON ELECTRIC CO 发明人 OOTSUKA AKIO
分类号 H01L29/73;H01L21/31;H01L21/331;H01L29/06 主分类号 H01L29/73
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