发明名称 TEST OF SEMICONDUCTOR WAFER
摘要 PURPOSE:To facilitate the test of the semiconductor wafer by a method wherein when an epitaxial active layer on the semiconductor wafer is to be etched, the prearranged area part of the active layer is also etched simultaneously to form a Schottky electrode, and the impurity atom concentration distribution at the interface of the active layer is measured. CONSTITUTION:The electric characteristic of an epitaxial layer consisting of a buffer layer 2, the active layer 3 having respectively different concentration and being formed on a semi-insulating substrate 1 is estimated using a step etch pattern A, a leak check pattern B and an FET pattern C. A Schottky barrier gate 16 in the FET pattern C is formed by recessing the active layer 3 and evaporating the Schottky metal, and in the recessing process of the active layer, a circular groove to form by evaporation the Schottky barrier electrode 17 of the pattern A therein is formed simultaneously. Accordingly the atom concentration distribution at the interface of the active layer and the buffer layer in the epitaxial layer can be obtained easily.
申请公布号 JPS56157041(A) 申请公布日期 1981.12.04
申请号 JP19800060851 申请日期 1980.05.08
申请人 FUJITSU LTD 发明人 OGASAWARA KAZUTO
分类号 H01L21/66;(IPC1-7):01L21/66 主分类号 H01L21/66
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