| 摘要 |
PURPOSE:To simplify a simultation model and a logical test device and shorten the time of generation for a test data, by synchronizing the asynchronous input of an FF circuit in a test of a logical circuit. CONSTITUTION:In case a logical device including an FF circuit is modeled into a combined circuit by a logical test device and then simulated, a test indication is given to an input line 3 and the logical value of the line 3 is changed from 0 to 1. As a result, the input lines 66 and 86 of a master latch 9 and a slave latch 10 are cut off from the asynchronous control signal applied from an input line 4 or 5. Thus the asynchronous control signal changes immediately an output 28 to logical value 0. However, in case the timing of this change is equal to the logical value 0 of the clock, the latches 9 and 10 latch the output 28 before a change of a selector 7 until the output changes again to logical value 0 after the end of supply of logical value 1 in the next timing of the clock. As a result, the asynchronous control signal is delayed until the time when the clock changes to logical value 0 from 1 to be synchronized. |
