| 摘要 |
PURPOSE:To accelerate the start of practical operation of an extended precision addition/subtraction instruction and to speed up the practical subtraction by providing two, upper and lower N-byte carry propagation adders and selecting outputs of these two adders. CONSTITUTION:Low-order mantissa parts are set to input registers 10 and 11 by a first addition/subtraction. The low-order mantissa part having a smaller characteristic part is inputted to a shifter 40, and the low-order mantissa part having a larger exponential part is inputted to a complement circuit 41. Outputs of the shifter 40 and the complement circuit 41 are inputted to carry propagation adders 50 and 51, and a second addition/subtraction is executed. In the case of real addition, the addition result set in a register 83 or 82 is selected by a selecting circuit 90 as the upper result, and the addition result set to a register 60 is unconditionally selected by a selecting circuit 91 as the lower result. In the case of real subtraction, the addition result of the register 83 or 82 is selected by the selecting circuit 90 as the upper result, and the addition result set to a register 61 or the register 60 is selected by the selecting circuit 91 as the lower result. |
