| 摘要 |
PURPOSE:To reduce debugging period by making the change in data on a bus line condition for stopping data storage into a stack in a bus monitoring device of a logic analyzer. CONSTITUTION:This device stops the storage of data into a stack 15 when the data on a bus line 6 changes in order of A B C. In this case, A, B, C are respectively set in set data 16, 17, 18. When the data A appears on the bus line 6, a comparator 7 detects this and sets a flip-flop 12 which outputs an enable signal 21 driving a comparator 8 of the next stage. Next, when the data B appears on the bus line 6, the output of the comparator 8 sets a flip-flop 13. If the data other than the data B appear, the flip-flop 12 is reset. Hence, only when the data appear in order of A B C on the bus line, a storage stop signal 23 is sent to the stack 15. Since the state of the bus line is detected by using the above-mentioned stop system, the debugging is carried out easily. |
