| 摘要 |
1. A semiconductor arrangement comprising a substrate (1) of the first conductivity type, a plurality of cells, each having a first zone (3) of the second conductivity type which is embedded in planar fashion in the substrate (1), and each having a second zone (4) of the first conductivity type which is embedded in planar fashion in the first zone (3), wherein, in the first zone (3) at the substrate surface, there is arranged a channel zone (5) which connects the substrate (1) and the second zone (4), and an insulating layer (6) arranged on the substrate surface and on which there is arranged a control electrode (7, 12) which covers at least the channel zone (5), characterized in that, between the first zone (3) of those cells which are adjacent to the edge of the semiconductor arrangement and the edge of the semiconductor arrangement, there is arranged at least one auxiliary electrode (8, 12, 13, 5) which is insulated from the substrate surface ; that the auxiliary electrode (8, 12, 13, 15) has a plurality of sections ; and that the section which is arranged closer to the edge of the semiconductor arrangement is spaced at a greater distance from the surface of the substrate than is the section which is arranged closer to the first zone (3). |
