RESET CIRCUIT AND PLL FREQUENCY SYNTHESIZER

摘要

PROBLEM TO BE SOLVED: To obtain a frequency synthesizer by eliminating a delay in a PLL operation time after releasing power saving so as not to delay a lockup time. SOLUTION: A control circuit 23 provided to a reset circuit 21 outputs a set signal S or a reset signal R to a delay circuit 22 to make an output signal SGC of the delay circuit 22 in matching with a level of a frequency setting signal DIV at that time when a power save signal PS is released. A discrimination circuit 24 does not output an L level output signal OUT to stop a phase comparator since the level of the frequency setting signal DIV matches the level of the output signal SGC of the delay circuit 22 in the case of releasing the power save signal PS. As a result, when the power save signal PS, the phase comparator can a start comparison to compare the phase of a reference signal with that of a comparison signal.