发明名称 TERNARY LEVEL INPUT CIRCUIT
摘要 PURPOSE:To obtain a circuit adapted to the IC, by connecting comparators consisting of the P channel MOS.FET and the N channel MOS.FET respectively to the power source through switching elements and by controlling these switching elements by the external pulse. CONSTITUTION:Comparator CMP5 consisting of P channel MOS.FET14 and resistance 16 is connected to power source VDD through switching element 18, and CMP6 consisting of N channel MOS.FET15 and resistance 17 is connected to the earth through swiching element 19. The bias voltage of 1/2 VDD is given to the gate of MOS.FET14 from bias resistance 2, and the input signal is supplied through switching element 20, and the input signal is set by setting switch 1. MOS.FETs 14 and 15 have threshold values higher and lower than 1/2 VDD, respectively, and outputs 7 and 8 are inputted to decoder 9 through memory circuit 13 and are decoded and are outputted from terminals 10-12. When timing signal 22 is H-level, switching elements 18-21 are turned off together, and current consumption becomes zero. When signal 22 is L-level, the ternary signal is outputted as shown in the table by the set value of setting switch 1.
申请公布号 JPS56153841(A) 申请公布日期 1981.11.28
申请号 JP19800055488 申请日期 1980.04.28
申请人 OKI ELECTRIC IND CO LTD 发明人 KAWAZOE AKIO
分类号 H04L25/03;H03K19/0175;H03K19/094;H03K19/20 主分类号 H04L25/03
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