| 摘要 |
<p>The invention is concerned with the problem of reducing the chip area occupied by volatile/nonvolatile dynamic RAM (random access memory) cells. A volatile/non-volatile dynamic RAM cell (30, 80) includes a storage capacitor (32) for volatilely storing binary information during normal RAM operation; an alterable-threshold storage capacitor (33A or 83) for non-volatilely storing the information in non-volatile fashion during poweroff conditions; and an energy barrier (33F or 45) between the two capacitors. Information can be restored to the volatile capacitor either by CCD charge transfer or by charge-pumped operation. The energy barrier facilitates efficient charge pumped restore of information. In one embodiment, the energy barrier is a high concentration substrate surface region (45) having the same conductivity type as the substrate. Alternatively, the alterable-threshold non-volatile capacitor and the energy barrier are provided by a split-gate capacitor (33) which has an alterable threshold non-volatile section (33A) (the non-volatile capacitor) and a non-alterable threshold section (33F) (the energy barrier). The cells may be arranged in an array. </p> |
