| 摘要 |
PURPOSE:To correct the phase error of 180 deg., by obtaining the signal, where the equivalent pulse part included in the composite synchronizing signal is eliminated, from the output terminal of the D type flip flop. CONSTITUTION:When the 7th clock of the signal is inputted to the clock input terminal of flip flop Q2 after reset inputs of flip flops Q2-Q5 are released, the output of AND gate G1 becomes high-level. The output of AND gate G2 becomes high- level, and D type flip flop Q7 is reset. When the composite synchronizing signal is inputted to composite synchronizing signal input terminal 22, Q7 is inverted by horizontal synchronizing signal B, and therefore, the output of AND gate G3 becomes high-level, and Q2-Q5 are reset. AND gate G1 is inverted, and the output of D type flip flop Q6 is inverted by the next clock input to clock signal input terminal 21, and therefore, reset pulses of Q2-Q5 are released at the instant. |
