| 摘要 |
PURPOSE:To obtain an efficient micro (mu) program PG control system by reading the same muPG word by continuing to generate the same (mu) address until an expected signal among asynchronizing signals is received and detected by muPG. CONSTITUTION:Selecting circuit 3 and address generating circuit 4 are indicated with a muPG word so that signal expecting register FF2 selects an asynchronizing signal among signals 1 asynchronous with a clock signal from the inside or outside of a data processor. Until the expected signal is received, circuit 4 generates the same address to read the same muPG word continuously and once the expected signal is received, circuit 3 updates the (mu) address to read the next muPG word from control memory CM5. After storing muPG, CM5 informs FF2 of which detected signal makes an advance of the step of muPG via latch register CMIR6 with the muPG word. Thus, there is no unnecessary step in receiving the expected signal and the efficient muPG control system is obtained. |
