| 摘要 |
PURPOSE:To eliminate an increase in delay due to wired OR by generating a carry- generation negation signal and carry-propagation negation signal at an input part, by performing wired AND by a carry look ahead circuit, and by selecting a data output result set up at an output part. CONSTITUTION:(n)-Bit binary data inputs A0-A3 and B0-B3, and arithmetic control inputs S0-S3 are inputted to input part 51-54 to generate a negation signal for the generation of a carry, carry generation signal, and negation signal for carry propagation as to every bit. Those negation signals for carry generation and propagation are applied to group carry signal generation part 55, which generate an (n)-bit group carry generation signal and group carry propagation signal to output the 1st or 2nd data from data output generation part 56 according to whether a carry from the low-order group is generated or not. Those 1st and 2nd output results are applied to data output selection parts 61-64 to select the output of output generation part 55, thereby preventing an increase in delay due to wired OR. |
