| 摘要 |
PURPOSE:To shorten the inspection time, and also, to decrease the hardware by compressing an inspection output pattern of (n) bit width to (m) bits by an exclusive OR network, and thereafter, inputting it to a multi-input feed-back type shift register (MISR). CONSTITUTION:A fault of a logic circuit for compressing an inspection output pattern as a signature is detected by an MISR 3 of (m) bits. That is, an inspection output pattern of (n) (n>m) bit width from a circuit to be inspected 1 such as an LSI, etc. is compressed to (m) bit width by a bit width compressing circuit 2 constituted of an exclusive OR network, and thereafter, inputted to the MISR 3 of (m) bit width. In such a way, a fault can be decided at a high speed without dropping the fault detection rate. |
