发明名称 FAULT INFORMING SYSTEM AMONG PLURAL DEVICES
摘要 <p>PURPOSE:To reduce the number of signal lines, by allotting a signal line to each device when a fault of a certain device is informed to each other among plural devices and then sharing the signal line as a fault information line from the relevant device to another one and vice versa. CONSTITUTION:The processors 1-4 are connected in a multiplex way via the signal lines A-D provided as many as the processors. A signal line is allotted to each processor to be used as a fault line which is used in common when the fault is informed from a relevant processor to another one and vice versa. Now in case the processor 1 has a fault, the output of the fault detecting circuit 15 changes from ''1'' to ''0'' to set the correspondence bit of the fault display register 16 at ''1''. At the same time, the bits of the registers 26-46 of processors 2-4 that cprrespond to the processor 1 are set at ''1'' through the signal line A. Each of processors 2-4 reads the contents of registers 26-46 to identify the fault of processor 1. Thus the number of the fault information lines is reduced among plural devices (processors).</p>
申请公布号 JPS56149627(A) 申请公布日期 1981.11.19
申请号 JP19800052886 申请日期 1980.04.23
申请人 HITACHI LTD;NIPPON TELEGRAPH & TELEPHONE 发明人 SHIYOUDA AKIO;YAMADA TAKAHIKO;SUYAMA MASATO
分类号 G06F11/30;G06F11/00;G06F13/00;G06F15/78 主分类号 G06F11/30
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