| 摘要 |
A semiconductor memory element includes a silicon substrate 1 of first conductivity type having a diffused region 3 of opposite conductivity type, a thin layer 5 of silicon oxide bridging the substrate 1 and the diffused region 3, and a charge trapping silicon nitride layer 6 formed to overlie the silicon oxide layer 5. A gate electrode 8 is provided on the silicon nitride layer 6. The diffused region 3 is provided with a surface doping concentration such that a surface portion of this diffused region inverts in conductivity type when a signal is applied to the gate electrode 8 to cause charge trapping in the silicone nitride layer 6 and the concentration of charge of opposite polarity attracted to the inverted region approaches degeneracy. In this state the memory element is written and to read the written state the flow of tunnel current is sensed through the PN diode formed by the inverted region. <IMAGE> |
