| 摘要 |
An MOS low voltage detector circuit includes a comparator which compares an internally generated reference voltage with an internally generated non-linear voltage. Both the reference voltage and the non-linear voltage are derived from a supply voltage, and the comparator generates an output whenever the divided down non-linear voltage falls below the reference voltage. This output is supplied to a series of regularly biased MOS inverter stages which not only amplify the comparator output but also amplify the inherent offset error in the comparator itself. Voltage compensating means may also be included in the comparator.
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