TEST TIME REDUCTION FOR MULTI-CHIP MODULES (MCM) AND FOR SYSTEM-IN-PACKAGES (SIP)

摘要

The invention relates to a semiconductor package having at least two electronic circuits and to methods for testing the semiconductor package. A first circuit has a digital input and a digital output and a test mode control line for setting the first semiconductor chip into a determined test mode. The digital input includes at least two parallel input paths and the digital output includes at least two parallel output paths. The at least two parallel input paths and at least two parallel output paths provide a corresponding number of inter-nal paths by which the first and second circuits can be tested at essentially the same time.