发明名称 CLOCK CONTROLLER
摘要 PURPOSE:To reduce power consumption of the integrated circuit, by stopping the system clock (SCK) and the basic clock (CK) when the data processing is not executed and by shortening the time of the transition state of the C-MOS constitution. CONSTITUTION:During the data processing, CK oscillating circuit 1 oscillates to supply basic CK11 to SCK generating circuit 2. Circuit 2 frequency-divides CK11 to supply SCK12 to data processing device 5. Device 5 executes various data processings synchronously with SCK12. During this time, power consumption based on the transition state of the C-MOS constitution in device 5 is increased in proportion to the frequency of SCK12. When device has nothing to execute, hold signal 15 is sent to CK control circuit 3. Circuit 3 receives signal 15 and sends oscillation stop signal 13 and SCK supply signal 14 to circuits 1 and 2 respectively to stop supplying of CK11 and SCK12. The operation state of the circuit is not changed, and device 5 becomes stable, and C-MOS has only a leak current, thus power consumption is reduced.
申请公布号 JPS56147220(A) 申请公布日期 1981.11.16
申请号 JP19800050855 申请日期 1980.04.17
申请人 NIPPON ELECTRIC CO 发明人 IWASAKI JIYUNICHI
分类号 H02J1/00;G06F1/04;G06F1/32 主分类号 H02J1/00
代理机构 代理人
主权项
地址