| 摘要 |
PURPOSE:To reduce the number of bits of one frame to 2/3 or more of conventional system, by inserting the delay element in series between the receiver and driver of the process input and output terminal station and prolonging the data input time from the terminal equipment. CONSTITUTION:A delay element 18 which is operated in synchronizing with the bit timing of transmission system is inserted in series between the receiver 10 and the driver 11 of the process input and output terminal station 5. When the final bit of the addressing time slot 7 is fetched to the address coincidence detector 12, the fetch of the input data to the process input and output terminal device corresponding to the address is started, and data is prepared for the input data register 15. The frame is made delayed with the element 18 by the time required for the data preparation. |
