发明名称 PULSE DELAYING CIRCUIT
摘要 PURPOSE:To obtain a pulse that possesses a desired delay time to an external trigger, by giving a phase comparison to each output delivered from delay lines equipped with taps with the external trigger and then selecting an output to compare it with the set value of delay extent through a comparator. CONSTITUTION:The output of the reference oscillator 1 is applied to the delay line 3 equipped with tap, and the output supplied from each tap is applied to the phase comparator 4 and the selecting circuit 5. The circuit 4 compares the tap output with the phase of the trigger input 2 and then applies the selection output to the circuit 5. The tap output selected through the circuit 5 is supplied to the counter 6 to be counted and then applied to the monostable multivibrator 9 when coincidence is secured with the set value of the delay extent setting circuit 7 through the comparator 8. In such way, a pulse possessing a desired delay time to an external trigger can be obtained through the vibrator 9.
申请公布号 JPS56146324(A) 申请公布日期 1981.11.13
申请号 JP19800048577 申请日期 1980.04.15
申请人 FUJITSU LTD 发明人 ITSUGAYA SAKAE
分类号 H03K5/13;H03K5/14;H03K17/28 主分类号 H03K5/13
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