| 摘要 |
<p>A structure of a non-volatile memory array is provided to supply a memory cell layout for a SONOS-type memory array that needs a smaller area and is more scalable, by including active regions and transistors formed between adjacent active regions such that the active regions form source/drain regions of the transistors. First and second active regions(210) are formed in a substrate, having substantially parallel lengthwise axes. A plurality of transistors are positioned between the first and second active regions wherein the first and second active regions function as source/drain region for the plurality of transistors. The plurality of transistors can be a SONOS transistor. Wordlines(222) have lengthwise axes substantially vertical to the lengthwise axes of the first and second active regions.</p> |
