| 摘要 |
PURPOSE:To prevent data error by providing a variable delay circuit of which the delay time increases when input signal frequency increases to the prestage of a data reproducing circuit system and increasing the phase margin of the reproducing circuit system. CONSTITUTION:The output signal of an equalizing circuit 13 is inputted via a variable delay circuit 25 to a pulse shaping circuit 14. The circuit 25 has such delay characteristics that the delay time increases with a rise in input frequency. A peak shift is produced in a read signal 20, and the phase advances. The quantity of this peak shift increases in proportion to the recording frequency. On the other hand, the delay time of the circuit 25 increases in proportion to the frequency of the input signal. Hence, it turns out that when viewed from the data reproducing circuit system the read signal 20 is compensated of the peak shift. Consequently, if the delay characteristics of the circuit 25 are adequately set, the read pulses 21 can assure sufficient phase margins. Hence, data errors are prevented by such constitution. |
