| 摘要 |
PURPOSE:To simplify structure by writing data readout by a single scanner, in a memory in series and by reading them in parallel to respective heads. CONSTITUTION:In write operation, a transfer clock is sent to synchronizing circuit 20 to drive address counter 22 and, at the same time, supplied to memory RAS generating circuit 26 to generate an RAS signal. The output signal of circuit 20 is supplied to memory generating circuit 15 via delay circuit 27 to generate a CAS signal. Next, as a memory write signal arrives, RAS and CAS are generated and address counter 22 is driven to write data in blocks 0-19 successively. In read mode, the write signal is held at the high level, and consequently outputs of block counter 12 and decoder 13 are both invalidated to supply the CAS signal to memory chips simultaneously. As a result, the contents of each address is made readable corresponding to the RAS signal to supply a line signal to heads H0-H11. |
