| 摘要 |
PURPOSE:To suppress the generation of irregularity of an integrated circuit at the time of assembly and to decrease the inductance of the integrated circuit by a method wherein at least one of the metal wirings between the gate electrodes of a transistor substrate and an input side circuit; and the metal wirings between drain electrodes and an output side circuit is used as mesh ribbon type metal wirings. CONSTITUTION:An input side circuit is formed of an input side matching circuit board 3 and a chip capacitor 4. Prescribed electrodes of the capacitor 4 are connected with gate electrodes 21 of a transistor substrate 2 by mesh ribbon type wirings 6 which are first metal wirings. An output side matching circuit board 5 is connected with drain electrodes 22 of the transistor substrate 2 by second metal wirings 7. Wereupon, the inductances LG between the electrodes 21 and the electrodes of the capacitor 4 are reduced in a high frequency band, particularly even in a quasi-mm frequency band of 20-30 GHz. Thereby, the irregularity of an integrated circuit at the time of assembly is suppressed and the inductance of the integrated circuit is decreased. |
