发明名称 FRAME PATTERN COLLATION SYSTEM
摘要 PURPOSE:To grasp the error rate of an input signal in a synchronized state, by preventing an out-of-frame state as much as possible against either one of a random error and a bust error caused by a momentary interruption, etc. CONSTITUTION:An input frame pattern at the time of collation and a frame pattern preceding by one frame are collated with each other by the frame-pattern collating circuit composed of correlation memory 11 and the 1st exclusive OR circuit 12. Frame-pattern collation algorithm switching circuit 20 is controlled with frame- synchronism state pulses supplied to frame-synchronism state pulse input terminal 16; when the pulse shows a synchronized state, is is made to switch and the frame- pattern collation algorithm is bn=an(+)an-1(+)bn-1. When the said pulse shows an out-of-frame state, on the other hand, the collation is done with bn=an(+)an-1.
申请公布号 JPS56144656(A) 申请公布日期 1981.11.11
申请号 JP19800046865 申请日期 1980.04.11
申请人 NIPPON ELECTRIC CO 发明人 KATOU YOSHIBUMI
分类号 H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/06
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