Circuit arrangement for correlating several isofrequentially stepped counting chains

摘要

A plurality of binary counters, each consisting of a primary and a secondary counting chain, are stepped by respective trains of clock pulses of like cadence but indeterminate phase relationship. The several primary counting chains are provided on their input sides with respective correlation circuits and on their output sides with respective sync generators, either of which is used for a concurrent restarting of both chains upon the attainment of a full count. A selection signal establishes one of the primary counting chains as the master by unblocking its sync generator while blocking its correlation circuit, the opposite being the case in all the other counters which are controlled from the unblocked sync generator through their respective correlation circuits. The primary and secondary chains of each counter work into a common comparator which detects any disparity in their readings and, in the event of such disparity, emits an alarm signal while also modifying the selection signal to designate a different primary chain as the master.