| 摘要 |
PURPOSE:To prevent malfunction occurring in case that a signal other than a BCD code is addressed, by providing an address error detection circuit to a memory circuit to which accessed directly with a BCD code. CONSTITUTION:A BCD code is inputted to address buffers 45 and 46 and then supplied to row decoder 42 and column decoder 43 via address signal lines 51 and 52. Decoders 42 and 43 consist of enhancement type FETs 31, 32, 33, and 34, and depletion type FET 35; only one decoder output 36 is made true in response to the BCD code input at any time, and the row line and column line of memory array 41 connected to it are selected to read the contents of a specific cell from output circuit 44. Address signal lines 51 and 52 are connected to address error detection circuit 49 composed of the same kind of circuit with the decoders and if a signal other than a BCD code is inputted, error detection output 50 is generated. |
