发明名称 TIME-DIVISION CHANNEL CONTINUITY TEST SYSTEM
摘要 PURPOSE:To test continuity under software control without providing an unnecessary testing device, by providing a connecting means of sending the contents of the specific output time slot of a switching network back to the input time slot that corresponds to this output time slot. CONSTITUTION:Under a command from a central processor, test data T is written in address (a) of signal transmitting memory 22. Control memory 24 stores this test data in time slot (i) at the input part of data extraction device C, which extracts and transfers only this data to data transfer device D via return channel 34. Then, data T inserted into time slot (i) is written by control memory 16 in primary channel memory 12, transferred to secondary channel memory 20' and further to the 2nd input time slot, and written in signal receiving memory 14', where it is compared with the contents of signal transmitting memory 22 to check the continuity state.
申请公布号 JPS56143746(A) 申请公布日期 1981.11.09
申请号 JP19800046152 申请日期 1980.04.10
申请人 FUJITSU LTD 发明人 MATSUURA YOSHIAKI;AOKI KENZOU;NARA TAKASHI;NOMURA YOSHITAKA
分类号 H04M3/26;H04M3/24;H04Q11/04 主分类号 H04M3/26
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