| 摘要 |
<p>PURPOSE:To reduce access to a main memory, by providing a bus coupler with a circuit monitoring whether the memory write request is successful or not and a circuit which rewrites the former data in memory with written-in data. CONSTITUTION:A plurality of processors PCs 1 are coupled with the main memory 5 via the bus coupler and bus 7 respectively. When the memory write-in request from PC1 to the memory 5 is produced on the bus 7, the montor circuit 21 judges if the data to the address is stored in the memory 30 in the bus coupler. If stored, the replacement circuit receives the instruction to fetch the data. When the data is fetched and a signal that the write-in to the main memory 5 is successuful on the bus 7 is generated, the circuit 22 replaces the data in the memory 30 with new data. Thus, the change of the data of the memory 5 is effected on the memory in the bus coupler, the number of times of access is reduced and the system performance is increased.</p> |
