| 摘要 |
PURPOSE:To achieve desired transfer speed without delaying the requested cycle time, by operating the values of 2nd timing and present timing stored at the data response processing and returning the response signal to the request device. CONSTITUTION:When the response controlling circuit 6 receives the response signal 13 from the memory controlling device 100, synchronism is taken, and the output signal 20 consisting of the 2nd timing signal 19 read out from the storage circuit 4, and the request reception signal 17, is compared with the present 2nd timing signal 19. If the result of comparison is in coincidence and it is in coincidence with the 1st timing 14, the response signal 16 is produced to the data request device. |
